Phase-locked loops (PLLs) are used in data communications and telecommunications applications to lock onto the frequency and phase of a signal. In particular, monolithic PLLs are often used in clock and data recovery (CDR) applications. A typical monolithic PLL includes a phase detector, a charge pump, a loop filter, and a voltage controlled oscillator (VCO) that produces a VCO signal. Monolithic PLLs used for CDR are typically divided into two categories; either a linear PLL, which uses a Hogge-type linear phase detector or a binary or “bang-bang” PLL, which uses an Alexander-type binary phase detector.
One performance characteristic of a PLL is the 3 decibel (dB) bandwidth frequency. The 3 dB bandwidth frequency is a measure of the frequency range within which the PLL is able to track frequency changes of the input signal. With typical linear PLLs, the 3 dB bandwidth frequency is a function of the phase detector gain, the charge pump gain, the VCO gain, and the loop zero resistance. The phase detector gain, the charge pump gain, and the loop zero resistance can each vary by ±20%, while the VCO gain often varies by 5-to-1 or more. When using a resonant inductance capacitance (LC)-type VCO, the wide variation in the VCO gain is due to the non-linear capacitance vs. voltage characteristic of monolithic variable capacitors (i.e., varactors) and the inverse square root dependence of the VCO frequency on the LC tank capacitance of the VCO.
The variation of the VCO gain in a linear PLL with an LC-type VCO can be reduced by limiting the voltage range that is used to tune the VCO. While limiting the voltage tuning range reduces the variation in VCO gain, it also limits the frequency range over which the VCO can be tuned and therefore, there is a tradeoff between the magnitude of variation in the VCO gain and the frequency range of a VCO.
In view of this, what is needed is a linear PLL that exhibits relatively constant gain and a wide frequency tuning range.